The present invention generally relates to a method for forming a fine pattern of a semiconductor device.
Due to the popularization of information media such as computers, semiconductor device technology has advanced rapidly. Semiconductor devices are required to operate at a high speed and to have a high storage capacity. As a result, manufacturing technology of semiconductor devices is required to manufacture a memory device of high capacity with improved integration, reliability and characteristics for accessing data.
In order to improve integration of the device, photolithography technology has developed to form fine patterns. The photolithography technology includes an exposure technology using chemically amplified Deep Ultra Violet (DUV) light sources such as ArF (193 nm) and VUV (157 nm), and a technology for developing photoresist materials suitable for the exposure light sources.
As a semiconductor device becomes smaller, it is important to control a critical dimension of a pattern line-width in the photolithography technology. Generally, the processing speed of semiconductor devices depends on the critical dimension of the pattern line-width. For example, when the size of the pattern line-width is decreased, the processing speed is increased to improve device performance.
However, it is difficult to form a line and space (L/S) pattern of less than 40 nm by a single exposure process in the photolithography process using an ArF exposer having a common numerical aperture of less than 1.2. Although an exposer having a high numerical aperture with a high index fluid material is used, it is impossible to form L/S pattern of less than 30 nm. When an exposure light source such as extreme ultra violet (EUV) (32 nm) is used in order to form a pattern of less than 30 nm, it is necessary to develop an exposer and resist suitable for the exposure light source, thereby increasing the manufacturing cost.
In order to improve resolution of photolithography technology and extend a process margin, a double patterning technology has been developed. The double patterning technology includes processes whereby a photoresist-coated wafer is respectively exposed by two masks, and then developed, thereby obtaining a complicated pattern, a dense pattern or an isolated pattern.
Since the double patterning technology uses two masks for patterning, the manufacturing cost and the turn-around-time are lower than those of a single patterning technology using a single mask, thereby degrading the throughput. When a pattern having a smaller pitch than a resolution limit of the exposer is formed in the cell region, exposed images are overlapped. As a result, the double patterning technology does not obtain a desired pattern. In alignment, overlays are mis-aligned.